Microprocessor and Interfacing free essay sample

Peripherals and Interfacing PIO 8255 The equal info yield port chip 8255 is additionally called as programmable fringe input-yield port. The Intel’s 8255 is intended for use with Intel’s 8-piece, 16-piece and higher ability chip. It has 24 information/yield lines which might be exclusively customized in two gatherings of twelve lines each, or three gatherings of eight lines. The two gatherings of I/O pins are named as Group An and Group B. Every one of these two gatherings contains a subgroup of eight I/O lines called as 8-piece port and another subgroup of four lines or a 4-piece port. In this manner Group A contains a 8-piece port An alongside a 4-piece port. C upper. PIO 8255 †¢ The port A lines are recognized by images PA0-PA7 while the port C lines are distinguished as PC4-PC7. Additionally, GroupB contains a 8-piece port B, containing lines PB0-PB7 and 4-piece port C with lower bits PC0-PC3. We will compose a custom article test on Chip and Interfacing or on the other hand any comparative subject explicitly for you Don't WasteYour Time Recruit WRITER Just 13.90/page The port C upper and port C lower can be utilized in blend as a 8-bitport C. †¢ Both the port C are relegated a similar location. Hence one may have either three 8-piece I/O ports or two 8-piece and two 4-piece ports from 8255. These ports can work freely either as info or as yield ports. This can be accomplished by programming the bits of an inward register of 8255 called as control word register ( CWR ). PIO 8255 †¢ The inward square outline and the pin setup of 8255 are appeared in fig. †¢ The 8-piece information transport cradle is constrained by the read/compose control rationale. The read/compose control rationale deals with the entirety of the inward and outer exchanges of the two information and control words. †¢ RD, WR, A1, A0 and RESET are the sources of info gave by the chip to the READ/WRITE control rationale of 8255. The 8-piece, 3-state bidirectional cushion is utilized to interface the 8255 inside information transport with the outside framework information transport. PIO 8255 †¢ This cradle gets or transmits information upon the execution of information or yield guidelines by the microchip. The control words or status data is additionally moved through the support. †¢ The sign portrayal of 8255 are quickly introduced as follows : †¢ PA7-PA0: These are eight port A lines that goes about as either hooked yield or cushioned info lines relying on the control word stacked into the control word register. †¢ PC7-PC4 : Upper snack of port C lines. They may go about as either yield hooks or information cushions lines. PIO 8255 This port additionally can be utilized for age of handshake lines in mode 1 or mode 2. †¢ PC3-PC0 : These are the lower port C lines, different subtleties are equivalent to PC7-PC4 lines. †¢ PB0-PB7 : These are the eight port B lines which are utilized as locked yield lines or supported information lines similarly as port A. †¢ RD : This is the info line driven by the microchip and ought to be low to demonstrate read activity to 8255. †¢ WR : This is an information line driven by the chip. A low on this line demonstrates compose activity. PIO 8255 †¢ CS : This is a chip select line. On the off chance that this line goes low, it empowers the 8255 to react to RD and WR signals, in any case RD and WR signal are ignored. †¢ A1-A0 : These are the location input lines and are driven by the chip. These lines A1-A0 with RD, WR and CS from the accompanying tasks for 8255. These location lines are utilized for tending to any of the four registers, I. e. three ports and a control word register as given in table underneath. †¢ in the event of 8086 frameworks, if the 8255 is to be interfaced with lower request information transport, the A0 and A1 pins of 8255 are associated with A1 and A2 separately. RD 0 RD 1 RD X 1 WR 1 WR 0 WR X 1 CS 0 CS 0 CS 1 0 A1 0 1 A1 0 1 A1 X A0 0 1 0 1 A0 0 1 0 1 A0 X Input (Read) cycle Port A to Data transport Port B to Data transport Port C to Data transport CWR to Data transport Output (Write) cycle Data transport to Port A Data transport to Port B Data transport to Port C Data transport to CWR Function Data transport tristated Data transport tristated Control Word Register PIO 8255. †¢ D0-D7 : These are the information transport lines those convey information or control word to/from the microchip. †¢ RESET : A rationale high on this line clears the control word register of 8255. All ports are set as information ports as a matter of course after reset. Square Diagram of 8255 (Architecture) ( cont.. ) †¢ 1. 2. 3. 4. †¢ It has a 40 pins of 4 gatherings. Information transport support Read Write control rationale Group An and Group B controls Port A, B and C Data transport cradle: This is a tristate bidirectional cushion used to interface the 8255 to framework databus. Information is transmitted or gotten by the cushion on execution of info or yield guidance by the CPU. Control word and status data are additionally moved through this unit. †¢ Block Diagram of 8255 (Architecture) ( cont.. ) Peruse/Write control rationale: This unit acknowledges control signals ( RD, WR ) and furthermore contributions from address transport and issues orders to singular gathering of control squares ( Group A, Group B). †¢ It has the accompanying pins. a) CS Chipselect : A low on this PIN empowers the correspondence among CPU and 8255. b) RD (Read) A low on this pin empowers the CPU to peruse the information in the ports or the status word through information transport cradle. †¢ Block Diagram of 8255 (Architecture) ( cont.. ) WR ( Write ) : A low on this pin, the CPU can compose information on to the ports or on to the control register through the information transport support. ) RESET: A high on this pin clears the control register and all ports are set to the info mode e) A0 and A1 ( Address pins ): These pins related to RD and WR pins control the determination of one of the 3 ports. †¢ Group An and Group B controls : These square get control from the CPU and issues orde rs to their separate ports. c) Block Diagram of 8255 (Architecture) ( cont.. ) †¢ Group A PA and PCU ( PC7 - PC4) †¢ Group B PCL ( PC3 PC0) †¢ Control word register must be composed into no read activity of the CW register is permitted. a) Port A: This has a 8 piece hooked/cradled O/P and 8 piece input lock. It very well may be customized in 3 modes mode 0, mode 1, mode 2. b) Port B: This has a 8 piece locked/supported O/P and 8 piece input hook. It very well may be modified in mode 0, mode1. Square Diagram of 8255 (Architecture). c) Port C : This has a 8 piece hooked information cradle and 8 piece out put locked/support. This port can be partitioned into two 4 piece ports and can be utilized as control signals for port An and port B. it tends to be modified in mode 0. Methods of Operation of 8255 (cont.. ) †¢ These are two fundamental methods of activity of 8255. I/O mode and Bit Set-Reset mode (BSR). †¢ In I/O mode, the 8255 ports fill in as programmable I/O ports, while in BSR mode just port C (PC0-PC7) can be utilized to set or reset its individual port bits. †¢ Under the I/O method of activity, further there are three methods of activity of 8255, in order to help various sorts of uses, mode 0, mode 1 and mode 2. Methods of Operation of 8255 (cont.. ) †¢ BSR Mode: In this mode any of the 8-bits of port C can be set or reset contingent upon D0 of the control word. The bit to be set or reset is chosen by bit select banners D3, D2 and D 1 of the CWR as given in table. I/O Modes : a) Mode 0 ( Basic I/O mode ): This mode is likewise called as fundamental info/yield mode. This mode gives basic info and yield capacities utilizing every one of the three ports. Information can be basically perused from and kept in touch with the info and yield ports separately, after suitable initialisation. D3 0 1 D2 0 1 0 1 D1 0 1 0 1 0 1 0 1 Selec ted bits of port C D0 D1 D2 D3 D4 D5 D6 D7 BSR Mode : CWR Format PA 8 2 5 PCU PCL PA6 PA7 PC4 PC7 PC0-PC3 PB PB0 PB7 8 2 5 PA PCU PCL PB PA PC PB0 PB7 All Output Port An and Port C going about as O/P. Port B going about as I/P Mode 0 Modes of Operation of 8255 (cont.. ) †¢ 1. The notable highlights of this mode are as recorded underneath: Two 8-piece ports ( port An and port B )and two 4-piece ports (port C upper and lower ) are accessible. The two 4-piece ports can be combinedly utilized as a third 8-piece port. Any port can be utilized as an info or yield port. Yield ports are locked. Info ports are not locked. A limit of four ports are accessible with the goal that general 16 I/O setup are conceivable. Every one of these modes can be chosen by programming a register inward to 8255 known as CWR. 2. 3. 4. †¢ Modes of Operation of 8255 (cont.. †¢ The control word register has two configurations. The main organization is legitimate for I/O methods of activity, I. e. modes 0, mode 1 and mode 2 while the subsequent arrangement is substantial for bit set/reset (BSR) method of activity. These arrangements are appeared in following fig. D7 1 D6 X D5 X D4 X D3 D2 D1 D0 0-Reset 0-for BSR mode Bit se lect banners D3, D2, D1 are from 000 to 111 for bits PC0 TO PC71-Set I/O Mode Control Word Register Format and BSR Mode Control Word Register Format PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3 8255A Pin Configuration = D0-D7 CS RESET 8255A A0 A1 RD PA0-PA7 PC4-PC7 PC0-PC3 PB0-PB7 Vcc WR GND Signals of 8255 3 Group A control 1 D0-D7 Data transport Buffer 8 piece int information transport 4 Group A Port A(8) PA0-PA7 Group A Port C upper(4) Group B Port C Lower(4) PC7-PC4 PC0-PC3 2 RD WR A0 A1 RESET CS Block Diagram of 8255 READ/WRITE Control Logic Group B control PB7-PB0 Group B Port B(8) D7 D6 D5 Mode for Port A D4 PA D3 PC U D2 Mode for PB D1 PB D0 PC L Mode Set banner 1-dynamic 0-BSR mode Group A 1 Input PC u 0 Output 1 Input PA 0 Output 00 mode 0 Mode 01 mode 1 Select of PA 10 mode 2 Group B PCL PB Mode Select 1 Input 0 Output 1 Input 0 Output 0 mode-